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Cypress Semiconductor /psoc63 /BLE /BLELL /DPLL_CONFIG

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Interpret as DPLL_CONFIG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DPLL_CORREL_CONFIG

Description

DPLL & CY Correlator configuration register

Fields

DPLL_CORREL_CONFIG

If MXD_IF_OPTION is 0: Not used

If CY_CORREL_EN is 1: [11:0] CY correl Access address compare mask for LSB 12 bits. Ideal value is 0xFFF [15:12] CY correl maximum number of allowed mismatched bits in access address. Ideal value is 0x0.

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data